1. Technical Field
This invention relates to a basic logic circuit from which a family of logic circuits can be developed to form logic networks using very large scale integration (VLSI) techniques.
2. Background Art
Existing data processing systems are largely comprised of pre-diffused logic networks. By simplifying the design of these networks, the cost of the systems can be reduced. To this end, networks comprised of general-purpose cells of the type described in U.K. Patent Application No. 2,025,688 may be used. This cell consists of emitter-coupled logic (ECL) circuits and is, therefore, mainly used in networks which must operate at high speeds but do not require high component densities. In applications of this type, master slices in which basic cells performing an elementary logic function such as NAND have been diffused are generally used. The master slice is then customized by appropriately interconnecting the cells to produce the desired network.
The type of basic cell that comprises a Transistor-Transistor-Logic (TTL) NAND gate as described in French patent No. 2,234,713 (U.S. Pat. No. 3,836,789) has the disadvantages of being slow and unsuitable for large-scale integration. This is due to the fact that many cells are required to enable this NAND gate to perform certain logic functions.
Also, the type of basic cell that comprises a Diode-Transistor-Logic (DTL) gate has the disadvantage, in addition to being unsuitable for large-scale integration, of exhibiting a poor immunity to noise because of its low switching level.
Today's technologies make it possible to manufacture integrated networks which have four levels of metallization. Thus, it is no longer necessary to provide separations between the cells of the network, which usually are arranged to form a matrix, to make the necessary interconnections as these can now be effected at the various levels of metallization. For example, the components of a given cell can be interconnected at the first level, the vertical wiring channels can be provided at the second level, and the horizontal ones at the third level. The size of the cell is determined, according to the number of cells to be interconnected, by the respective spacings of the horizontal and vertical wiring channels. As a result, the component density of logic networks comprised of conventional NAND gates can no longer be increased since each cell must occupy a specific area.
It is, therefore, an object of this invention to provide a basic logic circuit that can be used for realizing a general-purpose cell capable of performing many logic functions.
It is another object of this invention to provide such a logic circuit with a view to improving the cost-to-performance ratio of master slices used in logic networks.
It is still another object of this invention to provide such a circuit with a view to realizing very-large-scale-integration logic networks that require low supply voltages.